Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area reducing power consumption while maintaining frequency operation. Phase Locked Loop (PLL) an integral part circuits which operate at very high frequencies. Frequency Detector (PFD) first block PLL key in determining computational capacity PLL. The PFD has to be reduced minimize overall architecture used based Double Edged Triggered D Flip-Flop (DET-DFF), free dead zone. Stack, LECTOR, AVLS hybrid low-power approaches are implemented reduce DET-DFF architectures. PFDs power, delay product analysis performed using Cadence Virtuoso Spectre CMOS 180nm 90nm technology. A reduction up 32% been observed keeping transistor count minimum.